US 12,087,750 B2
Stacked-substrate FPGA semiconductor devices
Abhishek A. Sharma, Hillsboro, OR (US); Willy Rachmady, Beaverton, OR (US); Ravi Pillarisetty, Portland, OR (US); Gilbert Dewey, Beaverton, OR (US); and Jack T. Kavalieros, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Sep. 25, 2018, as Appl. No. 16/140,911.
Prior Publication US 2020/0098737 A1, Mar. 26, 2020
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/83896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1437 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit including a field programmable gate array (FPGA) device, the integrated circuit comprising:
a first semiconductor substrate;
a second semiconductor substrate over the first semiconductor substrate;
a dielectric layer between the first semiconductor substrate and the second semiconductor substrate;
a configurable logic block (CLB) including a logic transistor between the first semiconductor substrate and the second semiconductor substrate, and a memory cell over the second semiconductor substrate; and
a via directly connecting the logic transistor and the memory cell, the via disposed entirely through the second semiconductor substrate and extending above an uppermost surface of the second semiconductor substrate, the via over and vertically overlapping with the logic transistor and beneath and vertically overlapping with the memory cell, and the via having a bottommost surface above an uppermost surface of the logic transistor.