US 12,087,745 B2
Package structure and manufacturing method thereof
Wei-Yu Chen, New Taipei (TW); An-Jhih Su, Taoyuan (TW); Chi-Hsi Wu, Hsinchu (TW); Der-Chyang Yeh, Hsin-Chu (TW); Li-Hsien Huang, Hsinchu County (TW); Po-Hao Tsai, Taoyuan (TW); Ming-Shih Yeh, Hsinchu County (TW); and Ta-Wei Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Oct. 26, 2023, as Appl. No. 18/494,784.
Application 16/857,161 is a division of application No. 15/795,280, filed on Oct. 27, 2017, granted, now 10,636,775, issued on Apr. 28, 2020.
Application 18/494,784 is a continuation of application No. 17/567,169, filed on Jan. 3, 2022, granted, now 11,837,587.
Application 17/567,169 is a continuation of application No. 16/857,161, filed on Apr. 23, 2020, granted, now 11,217,570, issued on Jan. 4, 2022.
Prior Publication US 2024/0072021 A1, Feb. 29, 2024
Int. Cl. H01L 25/10 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/105 (2013.01) [H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/76802 (2013.01); H01L 23/3121 (2013.01); H01L 23/3142 (2013.01); H01L 23/481 (2013.01); H01L 23/5389 (2013.01); H01L 24/05 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/211 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a package structure, comprising:
providing a first semiconductor die;
forming a plurality of conductive pillars next to the first semiconductor die;
encapsulating the first semiconductor die and the plurality of conductive pillars in a first encapsulant;
placing a redistribution circuit structure over the first semiconductor die and the plurality of conductive pillars;
disposing a plurality of contact pads over the redistribution circuit structure;
connecting the plurality of contact pads to the plurality of conductive pillars through a plurality of conductive connectors, wherein in a cross-section of the package structure, a lateral offset between a sidewall of one of the plurality of conductive pillars and a sidewall of a respective one of the plurality of conductive connectors is about 50 μm to about 100 μm;
disposing a second semiconductor die over the redistribution circuit structure; and
encapsulating the second semiconductor die in a second encapsulant.