US 12,087,735 B2
Semiconductor device
Hirotaka Takeno, Yokohama (JP); Wenzhen Wang, Yokohama (JP); and Atsushi Okamoto, Yokohama (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by SOCIONEXT INC., Kanagawa (JP)
Filed on Mar. 24, 2021, as Appl. No. 17/210,743.
Application 17/210,743 is a continuation of application No. PCT/JP2018/036244, filed on Sep. 28, 2018.
Prior Publication US 2021/0210468 A1, Jul. 8, 2021
Int. Cl. H01L 25/065 (2023.01); G11C 5/14 (2006.01); H01L 27/02 (2006.01); H01L 23/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 27/0207 (2013.01); H01L 24/73 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06544 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first semiconductor chip; and
a second semiconductor chip,
wherein the first semiconductor chip includes:
a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface;
a first power supply line and a second power supply line arranged on the second principal surface of the substrate;
a power supply switch circuit arranged electrically between the first power supply line and the second power supply line;
a first via arranged in the substrate to extend from the first power supply line to the first principal surface and connected to the first power supply line; and
a second via arranged in the substrate to extend from the second power supply line to the first principal surface and connected to the second power supply line,
wherein the second semiconductor chip includes:
a third power supply line connected to the first via; and
a fourth power supply line connected to the second via.