US 12,087,730 B1
Multi-input threshold gate having stacked and folded planar capacitors with and without offset
Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); Debo Olaosebikan, San Francisco, CA (US); Tanay Gosavi, Portland, OR (US); Noriyuki Sato, Hillsboro, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/654,564.
Application 17/654,564 is a continuation of application No. 17/653,811, filed on Mar. 7, 2022.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/22 (2006.01); G11C 11/419 (2006.01); H01L 25/065 (2023.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01)
CPC H01L 25/0652 (2013.01) [G11C 11/221 (2013.01); G11C 11/419 (2013.01); H01L 28/55 (2013.01); H10B 12/20 (2023.02); H10B 12/48 (2023.02)] 26 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first capacitor, wherein the first capacitor has a first top electrode coupled to a first input, and a second terminal coupled to a node;
a second capacitor, wherein the second capacitor has a second top electrode coupled to a second input, and a second terminal coupled to the node; and
a third capacitor, wherein the third capacitor has a third top electrode coupled to a third input, and a second terminal coupled to the node, wherein the first capacitor, the second capacitor, and the third capacitor are planar capacitors that are arranged in a stacked and folded configuration, and wherein the first top electrode is coupled to the first input via a pedestal.