US 12,087,717 B2
Semiconductor package and methods of manufacturing a semiconductor package
Thomas Feil, Villach (AT); Danny Clavette, Greene, RI (US); Paul Ganitzer, Villach (AT); Martin Poelzl, Ossiach (AT); and Carsten von Koblinski, Villach (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Jul. 7, 2021, as Appl. No. 17/369,292.
Application 17/369,292 is a continuation of application No. 16/282,420, filed on Feb. 22, 2019, granted, now 11,081,457.
Claims priority of application No. 18158473 (EP), filed on Feb. 23, 2018.
Prior Publication US 2021/0335739 A1, Oct. 28, 2021
Int. Cl. H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/07 (2006.01); H01L 25/16 (2023.01); H01L 27/088 (2006.01)
CPC H01L 24/08 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/293 (2013.01); H01L 23/3135 (2013.01); H01L 23/3178 (2013.01); H01L 23/3185 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/73 (2013.01); H01L 24/82 (2013.01); H01L 24/96 (2013.01); H01L 25/072 (2013.01); H01L 25/16 (2013.01); H01L 27/088 (2013.01); H01L 23/3107 (2013.01); H01L 24/48 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/6834 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0233 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06182 (2013.01); H01L 2224/08137 (2013.01); H01L 2224/24105 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/245 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/73227 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a semiconductor wafer comprising separation regions arranged between component positions, the component positions comprising a first device region and a second device region, the first and second device regions each comprising an electronic device and being separated from one another by a non-device region;
forming a first metallization structure on a first surface of the semiconductor wafer;
forming at least one second trench in the first surface of the semiconductor wafer in the separation regions while the first metallization structure is exposed at the first surface;
applying a first epoxy layer to fill the at least one second trench with the first epoxy layer;
removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, to form a worked second surface of the semiconductor wafer and to reveal portions of the first epoxy layer in the separation regions;
applying a second metallization layer to the worked second surface;
operably coupling the second metallization layer to the first metallization structure; and
cutting through the first epoxy layer in the separation regions to form a plurality of separate semiconductor packages, each of the separate semiconductor packages comprising the first device region and the second device region.