US 12,087,708 B2
Chip protected against back-face attacks
Sebastien Petitdidier, La Terrasse (FR); Nicolas Hotellier, Jarrie (FR); Raul Andres Bianchi, Myans (FR); Alexis Farcy, La Ravoire (FR); and Benoit Froment, Grenoble (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Oct. 21, 2021, as Appl. No. 17/451,718.
Application 17/451,718 is a division of application No. 15/638,883, filed on Jun. 30, 2017, granted, now 11,183,468.
Claims priority of application No. 1658070 (FR), filed on Aug. 31, 2016.
Prior Publication US 2022/0045020 A1, Feb. 10, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/58 (2006.01); H01L 23/64 (2006.01); H03K 3/3565 (2006.01)
CPC H01L 23/576 (2013.01) [H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 23/481 (2013.01); H01L 23/49855 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/57 (2013.01); H01L 23/573 (2013.01); H01L 23/585 (2013.01); H01L 23/642 (2013.01); H03K 3/3565 (2013.01); H01L 23/293 (2013.01)] 20 Claims
OG exemplary drawing
 
6. A method for fabricating a semiconductor chip, the method comprising:
forming a first plurality of conducting pads at a front face of a substrate;
etching a rear face of the substrate to form a first plurality of openings under each of the first plurality of conducting pads, each of the first plurality of openings comprising walls and a bottom;
depositing a layer of dielectric on the walls and the bottom of each of the first plurality of openings;
forming a first conductive region at the rear face in each of the first plurality of openings, the first conductive region being capacitively connected to each of the first plurality of conducting pads through the dielectric on the bottom of each of the first plurality of openings; and
forming shallow trench isolation regions in the substrate at the front face of the substrate prior to forming the first plurality of conducting pads, wherein each of the shallow trench isolation regions is under a corresponding conducting pad of the first plurality of conducting pads.