US 12,087,693 B2
Non-conductive etch stop structures for memory applications with large contact height differential
Daniel R. Lamborn, Hillsboro, OR (US); Chuan Sun, Singapore (SG); and Qi Zhou, Liaoning (CN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/441,217
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
PCT Filed May 9, 2019, PCT No. PCT/CN2019/086118
§ 371(c)(1), (2) Date Sep. 20, 2021,
PCT Pub. No. WO2020/223945, PCT Pub. Date Nov. 12, 2020.
Prior Publication US 2022/0148971 A1, May 12, 2022
Int. Cl. H10B 43/50 (2023.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H10B 41/50 (2023.01); H10B 43/27 (2023.01)
CPC H01L 23/535 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76829 (2013.01); H01L 21/76895 (2013.01); H01L 23/5283 (2013.01); H10B 43/50 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a memory staircase structure, wherein first and second steps included in the staircase structure each comprises an insulator material layer and a conductive material layer;
an etch stop on the staircase structure, the etch stop including a high-k dielectric material, wherein the etch stop is a multi-layer structure that includes a first layer and a second layer, and one or both of the first and second layers comprises multiple phases;
an insulator fill material on the etch stop;
a first contact that passes through the etch stop and is on the conductive material layer of the first step, wherein the first contact has a first height; and
a second contact that passes through the etch stop and is on the conductive material layer of the second step, wherein the second contact has a second height that is more than 5× greater than the first height.