US 12,087,679 B2
Package core assembly and fabrication methods
Han-Wen Chen, Cupertino, CA (US); Steven Verhaverbeke, San Francisco, CA (US); Giback Park, San Jose, CA (US); Kyuil Cho, Santa Clara, CA (US); Kurtis Leschkies, San Jose, CA (US); Roman Gouk, San Jose, CA (US); Chintan Buch, Santa Clara, CA (US); Vincent Dicaprio, Pleasanton, CA (US); Bernhard Stonas, Hayward, CA (US); and Jean Delmas, Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on May 28, 2020, as Appl. No. 16/886,704.
Application 16/886,704 is a continuation in part of application No. 16/698,680, filed on Nov. 27, 2019, granted, now 11,862,546.
Prior Publication US 2021/0159160 A1, May 27, 2021
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/14 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 21/486 (2013.01); H01L 23/147 (2013.01); H01L 23/49827 (2013.01); H01L 23/49866 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device assembly, comprising:
a silicon core structure comprising:
a first side opposing a second side;
at least one via, the at least one via comprising a via surface extending between the first side and the second side; and
a metal cladding layer formed on and in direct contact with the first side, the second side, and the via surface, the metal cladding layer extending along the via surface between the first side and the second side;
a dielectric layer formed over the metal cladding layer on the first side, the second side, and the via surface, the dielectric layer extending along the metal cladding layer between the first side and the second side;
a conductive interconnection formed through the at least one via of the silicon core structure and having a surface exposed at the first side and the second side;
a first redistribution layer formed over the first side; and
a second redistribution layer formed over the second side, wherein the first redistribution layer and the second redistribution layer each have one or more conductive contacts formed thereon, and wherein the metal cladding layer is conductively coupled to ground or a reference voltage by at least one of the one or more conductive contacts formed on the first redistribution layer and the second redistribution layer, wherein the metal cladding layer has a thickness between about 100 nm and about 5 μm on substantially all exposed surfaces of the silicon core.