CPC H01L 23/49555 (2013.01) [H01L 21/56 (2013.01); H01L 23/3107 (2013.01); H01L 23/4951 (2013.01); H01L 23/4952 (2013.01); H01L 23/49524 (2013.01); H01L 23/49541 (2013.01); H01L 23/49551 (2013.01); H01L 23/49575 (2013.01); H01L 24/14 (2013.01); H01L 24/17 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 25/072 (2013.01); H01L 2924/181 (2013.01)] | 20 Claims |
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate comprising leads, the leads comprising:
lead terminals each comprising an outer side, an inner side opposite to the outer side, and a lower side connecting the outer side to the inner side;
lead steps; and
lead offsets extending between the lead steps so that at least some lead steps reside on different planes;
coupling a first electronic component to a first lead step of the lead steps;
coupling a second electronic component to a second lead step of the lead steps; and
providing an encapsulant encapsulating the first electronic component, the second electronic component, and portions of the substrate,
wherein:
the lead terminals each downwardly extend from a bottom side of an outermost lead step of the leads;
the lower sides of the lead terminals are exposed from a first side of the encapsulant; and
the encapsulant encapsulates the inner sides of the lead terminals.
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