| CPC H01L 21/76877 (2013.01) [H01L 21/76802 (2013.01); H01L 23/53238 (2013.01)] | 19 Claims |
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1. A method of forming a semiconductor structure, comprising:
forming a semiconductor device over a substrate;
forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, wherein the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer;
forming a conductive cap plate by performing an area selective deposition or a selective plating process that deposits a conductive material from a top surface of the connection-level metal interconnect structure without growing the conductive material from surface of the connection-level dielectric layer;
forming a line-and-via-level dielectric layer over the connection-level dielectric layer and directly on an entirety of a top surface of the conductive cap plate;
forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure;
selectively growing a conductive via structure consisting essentially of an elemental metal that is not copper from the top surface of the conductive cap plate without filling a line portion of the integrated line-and-via cavity and without filling an upper region of the via cavity portion such that a top surface; and
forming a copper-based conductive line structure that comprises copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity.
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