US 12,087,614 B2
Gap fill dielectrics for electrical isolation of transistor structures in the manufacture of integrated circuits
Michael Makowski, Beaverton, OR (US); Sudipto Naskar, Portland, OR (US); Ryan Pearce, Beaverton, OR (US); Nita Chandrasekhar, Portland, OR (US); Minyoung Lee, Vancouver, WA (US); and Christopher Parker, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 18, 2020, as Appl. No. 17/127,860.
Prior Publication US 2022/0199458 A1, Jun. 23, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/76224 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02274 (2013.01); H01L 21/0228 (2013.01); H01L 29/0649 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 10 Claims
OG exemplary drawing
 
1. One or more transistor structures, comprising:
a plurality of features comprising a semiconductor material;
a dielectric material in spaces between the features, wherein:
the dielectric material comprises silicon and oxygen;
a first aspect ratio of a first of the spaces between a first adjacent pair of the features is at least twice a second aspect ratio of a second of the spaces between a second adjacent pair of the features;
the dielectric material within the first aspect ratio further comprises a first concentration of nitrogen; and
the dielectric material within the second aspect ratio further comprises a second concentration of nitrogen, greater than the first concentration;
a gate electrode over a channel region of at least one of the features;
a source and a drain adjacent to the gate electrode, and coupled to opposite ends of the channel region.