CPC H01L 21/0337 (2013.01) [H01L 21/0332 (2013.01); H01L 21/76816 (2013.01); H01L 21/0338 (2013.01)] | 16 Claims |
1. A method for forming a semiconductor structure, comprising:
providing a to-be-etched layer, wherein the to-be-etched layer includes a plurality of first regions arranged in parallel along a first direction, a plurality of second regions arranged in parallel along the first direction and a plurality of third regions arranged in parallel along the first direction, and a second region of the plurality of second regions is adjacent to a first region of the plurality of first regions and a third region of the plurality of third regions;
forming a first core layer on the first region of the plurality of first regions, wherein the first core layer extends along a second direction perpendicular to the first direction;
forming a first sidewall spacer on sidewall surfaces of the first core layer;
forming a sacrificial layer covering a portion of the first sidewall spacer on the to-be-etched layer, wherein the sacrificial layer includes a plurality of initial first openings, an initial first opening of the plurality of initial first openings is on the second region, the initial first opening extends along the second direction, and a portion of the initial first opening exposes a portion of the first sidewall spacer on the second region;
removing the portion of the first sidewall spacer exposed by the portion of the initial first opening to form a first opening;
forming a second sidewall spacer in the first opening; and
forming a plurality of second openings in the sacrificial layer, wherein a second opening of the plurality of second openings exposes one of or both the portion of the first sidewall spacer and a portion of the second sidewall spacer.
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