US 12,087,391 B2
Drift compensation for codewords in memory
Marco Sforzin, Cernusco Sul Naviglio (IT); Paolo Amato, Treviglio (IT); Luca Barletta, Gallarate (IT); Marco Pietro Ferrari, Milan (IT); and Antonino Favano, Brolo (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 20, 2022, as Appl. No. 17/948,423.
Claims priority of provisional application 63/402,317, filed on Aug. 30, 2022.
Prior Publication US 2024/0071434 A1, Feb. 29, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 11/56 (2006.01)
CPC G11C 7/1063 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1069 (2013.01); G11C 11/5621 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device, comprising:
an array of memory cells; and
circuitry configured to:
sense a codeword stored in the array of memory cells;
determine a value of a cell metric of each memory cell of the sensed codeword, wherein the value of the cell metric of each of the memory cells is determined based on:
a summation of a threshold voltage value of each of the memory cells;
a mean of the threshold voltage values of the memory cells; and
a value proportional to the mean of the threshold voltage values of the memory cells;
determine which cell metric of each of the memory cells has a lowest value;
input the cell metric determined to have the lowest value to a Pearson detector; and
determine originally programmed data of the codeword using the Pearson detector.