US 12,087,388 B2
Method of performing internal processing operations with pre-defined protocol interface of memory device
Hak-Soo Yu, Hanam-si (KR); Namsung Kim, Yongin-si (KR); Kyomin Sohn, Yongin-si (KR); Seongil O, Suwon-si (KR); and Sukhan Lee, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 19, 2021, as Appl. No. 17/504,918.
Application 17/504,918 is a continuation of application No. 16/813,851, filed on Mar. 10, 2020, granted, now 11,158,357.
Claims priority of provisional application 62/816,509, filed on Mar. 11, 2019.
Claims priority of application No. 10-2019-0161673 (KR), filed on Dec. 6, 2019.
Prior Publication US 2022/0036929 A1, Feb. 3, 2022
Int. Cl. G11C 7/10 (2006.01); G11C 5/02 (2006.01); G11C 11/408 (2006.01); G11C 11/409 (2006.01)
CPC G11C 7/1045 (2013.01) [G11C 5/025 (2013.01); G11C 7/1039 (2013.01); G11C 11/4087 (2013.01); G11C 11/409 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a first memory region and a second memory region;
a processing-in-memory (PIM) engine configured to perform an internal processing operation on the first memory region;
a mode selector circuit configured to activate a processing mode selection signal for controlling the memory device to enter an internal processing mode when first addresses are received sequentially along with sequential write commands and when bit values of the first addresses match bit values of a first back-to-back address sequence of a PIM mode entering code associated with the sequential write commands, the PIM mode entering code being stored in the mode selector circuit; and
a command converter circuit configured to convert a received command into a PIM command to perform the internal processing operation in response to the activation of the processing mode selection signal.