US 12,087,387 B2
Methods and systems for managing read operation of memory device with single ended read path
Lava Kumar Pulluru, Bengaluru (IN); Poornima Venkatasubramanian, Bengaluru (IN); Manish Chandra Joshi, Bengaluru (IN); Ved Prakash, Bengaluru (IN); and Pushp Khatter, Bengaluru (IN)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 23, 2022, as Appl. No. 17/750,690.
Claims priority of application No. 202241011338 (IN), filed on Mar. 2, 2022.
Prior Publication US 2023/0282251 A1, Sep. 7, 2023
Int. Cl. G11C 7/10 (2006.01); H03K 3/037 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); H03K 3/0372 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device comprising:
at least one bitcell;
read circuitry coupled to the at least one bitcell; and
screening circuitry coupled to the read circuitry, wherein the screening circuitry includes:
a master slave flip-flop configured to:
store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and
a DOUT window controller coupled to the master slave flip-flop and configured to:
generate and control a master clock signal for the master latch to determine whether the at least one bitcell is a weak bitcell having an output that toggles beyond a closing edge of the master clock signal; and
generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.