US 12,087,385 B2
Method for obtaining circuit noise parameters and electronic device
Kang Zhao, Hefei (CN); and Weibing Shang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 26, 2022, as Appl. No. 17/953,297.
Application 17/953,297 is a continuation of application No. PCT/CN2022/107178, filed on Jul. 21, 2022.
Claims priority of application No. 202210685219.4 (CN), filed on Jun. 14, 2022.
Prior Publication US 2023/0013029 A1, Jan. 19, 2023
Int. Cl. G11C 7/08 (2006.01); G11C 29/02 (2006.01)
CPC G11C 7/08 (2013.01) [G11C 29/025 (2013.01); G11C 29/026 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for obtaining circuit noise parameters, comprising:
determining a plurality of circuits to be tested, each one of the plurality of circuits to be tested comprising one or more signal lines to be tested, and each one of the plurality of circuits to be tested having at least one operating state;
obtaining a parasitic capacitance between each one of the signal lines to be tested and all others of the signal lines to be tested, and determining a logic state of each one of the signal lines to be tested in each one of the plurality of circuits to be tested under each of the operating states;
determining a plurality of operating state combinations for the plurality of circuits to be tested, and determining one target operating state combination from the plurality of operating state combinations; and
under the target operating state combination, determining noise parameters of each one of the signal lines to be tested according to the logic state of each one of the signal lines to be tested and the parasitic capacitance, the noise parameters comprising external noise parameters caused by others of the plurality of circuits to be tested and internal noise parameters of a given one of the plurality of circuits to be tested corresponding to a given one of the plurality of signal lines to be tested;
wherein the determining a plurality of circuits to be tested comprises:
obtaining a plurality of functional circuits, and determining whether there is a logic state restriction relationship between different ones of the plurality of functional circuits;
determining the plurality of functional circuits having the logic state restriction relationship as one of the plurality of circuits to be tested; and
determining the plurality of functional circuits without the logic state restriction relationship as the plurality of circuits to be tested one by one respectively.