US 12,087,381 B2
Systems and methods for detecting and configuring lanes in a circuit system
Marian Cretu, Munich (DE); and Musaravakkam S. Krishnan, Saratoga, CA (US)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 24, 2021, as Appl. No. 17/357,181.
Prior Publication US 2021/0319841 A1, Oct. 14, 2021
Int. Cl. G11C 29/16 (2006.01); G06F 1/04 (2006.01); G06F 1/08 (2006.01); G06F 13/00 (2006.01); G06F 13/42 (2006.01); G11C 29/02 (2006.01); G06F 11/10 (2006.01)
CPC G11C 29/16 (2013.01) [G06F 13/4213 (2013.01); G11C 29/02 (2013.01); G06F 1/04 (2013.01); G06F 1/08 (2013.01); G06F 11/1048 (2013.01); G06F 13/00 (2013.01); G06F 13/423 (2013.01); G06F 13/4243 (2013.01); G06F 13/4256 (2013.01); G06F 2213/0024 (2013.01); G11C 29/023 (2013.01); G11C 29/025 (2013.01); G11C 29/028 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An electronic circuit system comprising:
a main device that generates first and second strobe signals and a clock signal, wherein the main device comprises a processing integrated circuit;
peripheral devices, wherein each of the peripheral devices comprises a memory integrated circuit; and
lanes, wherein a first one of the peripheral devices uses the first strobe signal with the clock signal to generate a first output signal in a first lane one of the lanes;
wherein a second one of the peripheral devices uses the second strobe signal with the clock signal to generate a second output signal in a second one of the lanes,
wherein the main device determines if the first one of the peripheral devices is coupled to the main device through the first one of the lanes based on the first output signal, wherein the main device determines if the second one of the peripheral devices is coupled to the main device through the second one of the lanes based on the second output signal, and wherein the main device detects a number of the lanes that are coupled to the peripheral devices and that are active in the electronic circuit system.