CPC G11C 16/3477 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/102 (2013.01); G11C 16/34 (2013.01); G11C 16/3418 (2013.01); G11C 16/3445 (2013.01)] | 20 Claims |
1. A memory device comprising:
a plurality of memory cells connected to each word line, among a plurality of word lines;
a peripheral circuit configured to perform a program operation on selected memory cells that are connected to a selected word line, among the plurality of word lines; and
a control logic configured to control the peripheral circuit to perform the program operation on the selected memory cells after performing a pre-program operation that increases a threshold voltage of over-erasure cells, among adjacent memory cells that are connected to an adjacent word line, having a threshold voltage of an over-erasure state that is lower than a threshold voltage of an erasure state, to the threshold voltage of the erasure state,
wherein the adjacent word line is a word line that is next to the selected word line;
wherein the control logic performs an over-erasure cell sensing operation before the pre-program operation on the over-erasure cells; and
wherein the over-erasure cell sensing operation:
senses threshold voltages of the adjacent memory cells; and
determines memory cells that have threshold voltages that are lower than an over-erasure verify voltage as the over-erasure cells among the adjacent memory cells.
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