US 12,087,373 B2
Non-volatile memory with optimized erase verify sequence
Yi Song, San Jose, CA (US); Lito De La Rama, San Jose, CA (US); and Xiaochen Zhu, Milpitas, CA (US)
Assigned to SanDisk Technologies LLC, Austin, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jul. 26, 2022, as Appl. No. 17/873,617.
Prior Publication US 2024/0047000 A1, Feb. 8, 2024
Int. Cl. G11C 16/00 (2006.01); G11C 16/04 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 16/0483 (2013.01); G11C 16/16 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A non-volatile storage apparatus, comprising:
a group of non-volatile memory cells; and
a control circuit connected to the memory cells, the control circuit is configured to apply doses of erasing to the group and perform erase verify between pairs of successive doses of erasing, the control circuit is configured to perform the erase verify by:
separately performing erase verify for multiple portions of the group between successive doses of erasing in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group,
aborting the performing of erase verify prior to completion of erase verify for all of the portions of the group between the successive doses of erasing in response to a cumulative number of erase errors for all portions of the group already erase verified exceeding a limit, the limit is a maximum number of erase errors for the group of non-volatile memory cells, and
completing erase verify for all portions of the group between the successive doses of erasing in response to the cumulative number erase errors for all portions of the group already erase verified not exceeding the limit.