US 12,087,370 B2
Storage system for enhancing data valid windows of signals
TongSung Kim, Seongnam-si (KR); Dae Hoon Na, Seoul (KR); Jung-June Park, Seoul (KR); Dong Ho Shin, Hwaseong-si (KR); Byung Hoon Jeong, Hwaseong-si (KR); and Young Min Jo, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 22, 2023, as Appl. No. 18/212,825.
Application 18/212,825 is a continuation of application No. 17/379,109, filed on Jul. 19, 2021, granted, now 11,699,492.
Claims priority of application No. 10-2020-0135852 (KR), filed on Oct. 20, 2020.
Prior Publication US 2023/0335203 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 1/10 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G11C 16/32 (2013.01) [G06F 1/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/06562 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A storage system, comprising:
a memory controller configured to provide a clock signal;
a buffer including:
a first duty cycle corrector configured to receive the clock signal and a chip selection signal from the memory controller and perform a first duty correction operation on the clock signal using a first data code and output a first corrected clock signal,
a register configured to store the first data code regarding the chip selection signal, and
a sampler configured to receive a data signal and a data strobe signal regarding the data signal, and output a data stream; and
a nonvolatile memory, including:
a second duty cycle corrector configured to receive the first corrected clock signal from the buffer and perform a second duty correction operation on the first corrected clock signal using a second data code and output a second corrected clock signal,
a second data code generation circuit configured to generate the second data code based on the second corrected clock signal, and
a data strobe signal generator configured to generate the data strobe signal based on the second corrected clock signal and provide the data strobe signal to the buffer.