	US 12,087,367 B2
	Non-volatile memory device and method of operating the same
Dong-Hun Kwak, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 15, 2023, as Appl. No. 18/450,241.
Application 18/450,241 is a continuation of application No. 18/108,085, filed on Feb. 10, 2023.
Application 18/108,085 is a continuation of application No. 17/949,752, filed on Sep. 21, 2022, granted, now 11,763,894.
Application 17/949,752 is a continuation of application No. 17/665,049, filed on Feb. 4, 2022, granted, now 11,594,286, issued on Feb. 28, 2023.
Application 17/665,049 is a continuation of application No. 16/935,559, filed on Jul. 22, 2020, granted, now 11,276,472, issued on Mar. 15, 2022.
Application 16/935,559 is a continuation in part of application No. 16/547,416, filed on Aug. 21, 2019, granted, now 11,217,314, issued on Jan. 4, 2022.
Claims priority of application No. 10-2018-0160352 (KR), filed on Dec. 12, 2018.
Prior Publication US 2023/0386581 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)

CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)]

27 Claims

1. A non-volatile memory device comprising:

a memory cell array comprising a plurality of word lines; and

a control logic circuit configured to apply a first target voltage level to a selected word line as a selected word line voltage for a first sensing operation in a first sensing time and apply a second target voltage level to the selected word line as the selected word line voltage for a second sensing operation in a second sensing time,

the control logic circuit further configured to

set the selected word line voltage to be a first voltage level in a first section of the first sensing time,

set the selected word line voltage to be a second voltage level in a second section of the first sensing time which follows the first section of the first sensing time, wherein the second voltage level is less than the first voltage level,

set the selected word line voltage to be the first target voltage level in a third section of the first sensing time which follows the second section of the first sensing time, wherein the first target voltage level is greater than the second voltage level,

set the selected word line voltage to be a third voltage level in a first section of a second sensing time which follows the third section of the first sensing time, and

set the selected word line voltage to be the second target voltage level in a second section of the second sensing time which follows the first section of the second sensing time,

wherein the first target voltage level is greater than the second target voltage level, and

wherein the second target voltage level is greater than the third voltage level.