	US 12,087,363 B2
	Control gate signal for data retention in nonvolatile memory
Abhijith Prakash, Milpitas, CA (US); and Anubhav Khandelwal, San Jose, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Feb. 14, 2023, as Appl. No. 18/109,466.
Application 18/109,466 is a continuation of application No. 17/191,474, filed on Mar. 3, 2021, granted, now 11,605,430.
Prior Publication US 2023/0186993 A1, Jun. 15, 2023
Int. Cl. G11C 11/00 (2006.01); G11C 11/18 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)

CPC G11C 16/08 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/32 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)]

6 Claims

1. A method of delaying charge leakage in a word line of a nonvolatile memory, comprising:

storing data in a plurality of nonvolatile memory cells configured to store multiple data states;

using a word line to access selected ones of the non-volatile memory cells;

supplying a control gate signal on a control gate line;

controlling the conductivity of a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line;

when entering a non-ON mode, placing all of word line switches in a nonconducting state and charging the control gate line to a charged potential.