US 12,087,361 B2
Memory device and operating method thereof
Bilal Ahmad Janjua, Suwon-si (KR); Jongryul Kim, Dangjin-si (KR); Venkataramana Gangasani, Suwon-si (KR); and Jungyu Lee, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 2, 2023, as Appl. No. 18/177,320.
Application 18/177,320 is a continuation of application No. 16/871,481, filed on May 11, 2020, granted, now 11,615,841.
Claims priority of application No. 10-2019-0131416 (KR), filed on Oct. 22, 2019.
Prior Publication US 2023/0207007 A1, Jun. 29, 2023
Int. Cl. G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/003 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01); H10B 63/24 (2023.02); H10B 63/84 (2023.02); H10N 70/231 (2023.02); H10N 70/8413 (2023.02); H10N 70/8828 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a plurality of memory cells disposed in locations in which a plurality of word lines and a plurality of bit lines intersect each other;
a decoder circuit configured to determine at least one of the plurality of memory cells to be a selected memory cell in response to an address; and
a program circuit configured to generate a sampling current of which a magnitude decreases as resistance of the selected memory cell increases during a sampling period, and to generate a programming current based on the sampling current during a programming period, in a programming operation for the selected memory cell.