US 12,087,357 B2
Multi-port memory architecture
Yew Keong Chong, Austin, TX (US); Sriram Thyagarajan, Austin, TX (US); Andy Wangkun Chen, Austin, TX (US); Arjun Singh, Bangalore (IN); and Ayush Kulshrestha, New Delhi (IN)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Jun. 20, 2022, as Appl. No. 17/844,551.
Prior Publication US 2023/0410896 A1, Dec. 21, 2023
Int. Cl. G11C 11/412 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port; and
read-write circuitry coupled to the read-write port, wherein the read-write circuitry comprises:
a column multiplexer coupled to the read-write port; and
write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle, wherein the write-drive logic comprises a write driver coupled to the column multiplexer, and wherein the read-sense logic comprises a first sense amplifier coupled to the column multiplexer.