US 12,087,353 B2
Burst read with flexible burst length for on-chip memory
Edward Martin McCombs, Jr., Austin, TX (US); Andrew David Tune, Dronfield (GB); Sean James Salisbury, Dendron (GB); Rahul Mathur, Austin, TX (US); Hsin-Yu Chen, Austin, TX (US); and Phani Raja Bhushan Chalasani, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Aug. 11, 2022, as Appl. No. 17/885,709.
Prior Publication US 2024/0055047 A1, Feb. 15, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/408 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory, comprising:
an array of random access memory storage elements, including selectable rows and groups of selectable columns, configured to output a selected number of words in response to a row select signal and a sequence of column select signals; and
circuitry configured to:
receive a burst read request including a memory address and a burst address indicating the selected number of words,
generate the row select signal based on the memory address,
generate the sequence of column select signals based on the burst address, and
provide the row select signal and the sequence of column select signals to the array,
where:
the sequence of column select signals is provided to each group of selectable columns, and each word of the selected number of words is formed from one bit output from each group of selectable columns,
each group includes a same number of selectable columns, and a total number of selectable words is the same as the number of selectable columns in each group, and
the selected number of words is less than the total number of selectable words.