US 12,087,351 B2
Bit line sense amplifier and memory device including the same
Seongjin Cho, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 3, 2022, as Appl. No. 17/857,015.
Claims priority of application No. 10-2021-0136693 (KR), filed on Oct. 14, 2021.
Prior Publication US 2023/0121199 A1, Apr. 20, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a plurality of memory cells;
a plurality of bit line sense amplifiers connected to the plurality of memory cells through a plurality of bit lines and a plurality of complementary bit lines; and
a control logic configured to control the plurality of bit line sense amplifiers to execute a first read operation and a second read operation of reading data stored in a portion of the plurality of memory cells,
wherein the plurality of bit line sense amplifiers are configured to:
in the first read operation, invert the data stored in the portion of the plurality of memory cells, and output the inverted data, and
in the second read operation, output the data stored in the portion of the plurality of memory cells.