| CPC G11C 11/40618 (2013.01) [G11C 11/40611 (2013.01); G11C 11/40615 (2013.01); G11C 11/4093 (2013.01)] | 20 Claims |
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1. A memory device comprising:
a memory cell array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns;
a row select circuit connected to the plurality of rows;
a refresh controller configured to control the row select circuit to apply a refresh operating voltage to at least one row; and
a memory control logic configured to decode a command received from a memory controller and to output a refresh command and external refresh address information,
wherein the refresh controller controls the row select circuit to perform one of an external refresh operation and an internal refresh operation, based on the refresh command that is output from the memory controller and based on whether a first row-hammering row address of the internal refresh operation is identical with a second row-hammering row address of the external refresh operation.
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