CPC G09G 3/2092 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/041 (2013.01)] | 20 Claims |
1. A display panel, comprising a gate driving circuit, a plurality of clock signal lines, a timing controller and a plurality of anti-cross-row circuits, wherein
the timing controller is configured to provide a first clock signal;
the plurality of anti-cross-row circuits are connected with the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal provided by the timing controller to a second clock signal, and output the second clock signal to the plurality of clock signal lines, wherein a falling duration of a falling edge of the second clock signal is less than a falling duration of a falling edge of the first clock signal;
the gate driving circuit comprises a plurality of shift register units that are cascaded and is connected with the plurality of clock signal lines, respectively, and the gate driving circuit is configured to output the second clock signal as an output signal line by line; and
each of the plurality of anti-cross-row circuits comprises at least one resistor and at least one inductor.
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