US 12,087,195 B2
Source amplifier having first and second mirror circuits and display device including the same
Taek Su Kwon, Suwon-si (KR); Woojoo Kim, Seoul (KR); and Dongwook Suh, Bucheon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 24, 2022, as Appl. No. 17/679,436.
Claims priority of application No. 10-2021-0084204 (KR), filed on Jun. 28, 2021.
Prior Publication US 2022/0415230 A1, Dec. 29, 2022
Int. Cl. G09G 3/3275 (2016.01); G09G 3/20 (2006.01)
CPC G09G 3/20 (2013.01) [G09G 2310/027 (2013.01); G09G 2310/0291 (2013.01); G09G 2320/0252 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A source amplifier configured to output a data voltage to a display panel based on a first driving voltage, a second driving voltage, a first input voltage, and a second input voltage, the source amplifier comprising:
a first circuit configured to generate a first current, a second current, a third current, and a fourth current based on the first driving voltage, the second driving voltage, the first input voltage applied to a gate of a fourth p-type transistor, directly connected to a set of p-type transistors, and the second input voltage applied to a gate of a fourth n-type transistor, directly connected to a set of n-type transistors, and to output the data voltage to an output terminal of the source amplifier based on the first to fourth currents; and
a second circuit connected with the first circuit, and configured to supply a fifth current to the output terminal of the source amplifier based on the first driving voltage, the second driving voltage, and the second input voltage, the second circuit including:
a first mirror circuit connected with a first terminal to which the first driving voltage is applied, and configured to supply a sixth current to the output terminal; and
a second mirror circuit connected with a second terminal to which the second driving voltage is applied, and configured to supply a seventh current from the output terminal to the second terminal;
wherein the first mirror circuit includes:
a first p-type transistor connected between the first terminal and the second circuit;
a second p-type transistor directly connected between the first terminal and a gate of the first p-type transistor; and
a third p-type transistor connected between the gate of the first p-type transistor and the second circuit;
wherein the second mirror circuit includes:
a first n-type transistor directly connected between the second circuit and the second terminal;
a second n-type transistor connected between a gate of the first n-type transistor and the second terminal; and
a third n-type transistor connected between the gate of the first n-type transistor and the second circuit, and wherein:
the second p-type transistor includes a gate to which a first enable signal is applied,
the third p-type transistor includes a gate to which a second enable signal is applied, and
the first enable signal and the second enable signal are complementary.