US 12,086,972 B2
Optimizing memory reads when computing video quality metrics
Deepa Palamadai Sundar, Sunnyvale, CA (US); Visalakshi Vaduganathan, Fremont, CA (US); and Harikrishna Madadi Reddy, San Jose, CA (US)
Assigned to META PLATFORMS, INC., Menlo Park, CA (US)
Filed by Meta Platforms, Inc., Menlo Park, CA (US)
Filed on Aug. 4, 2021, as Appl. No. 17/394,268.
Claims priority of provisional application 63/061,692, filed on Aug. 5, 2020.
Prior Publication US 2022/0046254 A1, Feb. 10, 2022
Int. Cl. G06T 7/00 (2017.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 17/17 (2006.01); H04N 19/103 (2014.01); H04N 19/117 (2014.01); H04N 19/147 (2014.01); H04N 19/176 (2014.01); H04N 19/182 (2014.01); H04N 19/36 (2014.01); H04N 19/40 (2014.01); H04N 19/523 (2014.01); H04N 21/44 (2011.01)
CPC G06T 7/0002 (2013.01) [G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 17/17 (2013.01); H04N 19/103 (2014.11); H04N 19/117 (2014.11); H04N 19/147 (2014.11); H04N 19/176 (2014.11); H04N 19/182 (2014.11); H04N 19/36 (2014.11); H04N 19/40 (2014.11); H04N 19/523 (2014.11); H04N 21/44008 (2013.01); G06T 2207/10016 (2013.01); G06T 2207/30168 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A system, comprising:
a set of caches of an application-specific integrated circuit configured to store neighbor pixel data for edge width searches of pixels comprising a frame of a video being analyzed for source video quality, comprising:
a first level cache to store pixel data comprising future neighbors and processing blocks;
a left neighbor second level directional cache to store left neighbors;
a vertical neighbor second level directional cache to store vertical neighbors; and
a right neighbor second level directional cache to store right neighbors; and
a kernel of the application-specific integrated circuit configured to retrieve corresponding neighbor pixel data for pixels comprising a current processing block of the frame from a subset of the set of caches and simultaneously perform, by processing in parallel, edge width searches in a plurality of search directions, using neighbor data from the first level cache and the second level directional caches in each of the plurality of search directions, for pixels comprising the current processing block to determine corresponding pixel edge width values used for computing a blurriness video quality metric based on pixel spread, wherein a filtering stage comprising the kernel is configured to determine the plurality of edge width search directions.