US 12,086,954 B2
Display apparatus
Yuki Okamoto, Kanagawa (JP); and Tatsuya Onuki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Appl. No. 17/768,726
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Oct. 19, 2020, PCT No. PCT/IB2020/059794
§ 371(c)(1), (2) Date Apr. 13, 2022,
PCT Pub. No. WO2021/084367, PCT Pub. Date May 6, 2021.
Claims priority of application No. 2019-199936 (JP), filed on Nov. 1, 2019.
Prior Publication US 2024/0144421 A1, May 2, 2024
Int. Cl. G06T 3/40 (2024.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G06T 1/20 (2006.01); G06T 3/4046 (2024.01); G09G 3/36 (2006.01); G09G 3/32 (2016.01)
CPC G06T 3/4046 (2013.01) [G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G06T 1/20 (2013.01); G09G 3/3688 (2013.01); G09G 3/32 (2013.01); G09G 2300/023 (2013.01); G09G 2340/0407 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A display apparatus comprising:
a first layer and a second layer stacked with each other,
wherein the first layer comprises a data driver circuit and an arithmetic circuit,
wherein the second layer comprises a display portion and a memory circuit,
wherein a neural network is configured in the arithmetic circuit,
wherein the data driver circuit has a region overlapping with the display portion,
wherein the arithmetic circuit has a region overlapping with the memory circuit,
wherein the memory circuit is configured to hold first image data, and
wherein the arithmetic circuit is configured to read out the first image data held in the memory circuit from the memory circuit, perform arithmetic processing on the first image data using the neural network to generate second image data, and supply the second image data to the data driver circuit.