US 12,086,899 B2
Graphics processing unit with selective two-level binning
Anirudh R. Acharya, San Diego, CA (US); Ruijin Wu, San Diego, CA (US); and Paul E. Ruggieri, Boxborough, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/032,268.
Claims priority of provisional application 63/062,770, filed on Aug. 7, 2020.
Prior Publication US 2022/0044350 A1, Feb. 10, 2022
Int. Cl. G06T 1/20 (2006.01); G06F 9/48 (2006.01); G06T 1/60 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 9/4893 (2013.01); G06T 1/60 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method comprising:
based on performance data indicating a two-level binning condition has been met,
patching a pending command buffer to be executable in a two-level binning mode, wherein;
the performance data is indicative of temperature or power consumption of a device;
the two-level binning mode is one of two or more binning modes executable by a graphics processing unit (GPU), the two or more binning modes including a single-level binning mode and the two-level binning mode; and
the two-level binning mode includes:
dividing an image frame associated with the pending command buffer into a plurality of coarse bins; and
for each coarse bin of the plurality of coarse bins:
dividing the coarse bin into a plurality of fine bins; and
rendering primitives associated with the pending command buffer based on how the primitives intercept the plurality of fine bins of the coarse bin; and
with the GPU, executing the pending command buffer in the two-level binning mode.