| CPC G06N 3/04 (2013.01) [G06F 17/153 (2013.01); G06F 17/16 (2013.01); G06N 3/08 (2013.01); G06T 9/002 (2013.01); G06F 9/3001 (2013.01)] | 20 Claims |
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1. A processor, comprising:
a first tile,
a second tile,
a memory, and
a bus,
the bus being connected to:
the memory,
the first tile, and
the second tile,
the first tile comprising:
a first weight register,
a second weight register,
an activations buffer,
a first multiplier, and
a second multiplier,
the first tile being configured to perform a convolution of an array of activations with a kernel of weights, the performing of the convolution comprising, in order:
forming a tensor product of the kernel with a first subarray of the array of activations;
forming a tensor product of the kernel with a second subarray of the array of activations, the second subarray being offset from the first subarray by n array elements in a first direction, n being a positive integer; and
forming a tensor product of the kernel with a third subarray of the array of activations, the third subarray being offset from the second subarray by one array element in a second direction, perpendicular to the first direction,
wherein the second subarray and the third subarray are spaced apart from an end of a row of the array of activations.
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