US 12,086,686 B2
Provisioning functional-level information to be utilized in gate-level processing of quantum circuits
Amir Naveh, Haifa (IL); Shmuel Ur, Shorashim (IL); Yehuda Naveh, Tel-Aviv Yafo (IL); Ofek Kirzner, Haifa (IL); Ravid Alon, Tel Aviv (IL); Tal Goren, Kibbutz Nahsholim (IL); and Nir Minerbi, Haifa (IL)
Assigned to CLASSIQ TECHNOLOGIES LTD., Tel Aviv (IL)
Filed by Classiq Technologies LTD., Tel Aviv (IL)
Filed on Oct. 12, 2021, as Appl. No. 17/450,583.
Prior Publication US 2023/0112525 A1, Apr. 13, 2023
Int. Cl. G06N 10/00 (2022.01); G06F 8/41 (2018.01)
CPC G06N 10/00 (2019.01) [G06F 8/41 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method to be implemented at a gate-level processing component, wherein the gate-level processing component is configured to compile gate-level representations of quantum circuits to thereby synthesize respective executable circuits that can be executed by a quantum computer, the method comprising:
obtaining a gate-level representation of a quantum circuit, wherein the gate-level representation comprises a set of quantum gates defining operations on a set of qubits, wherein the gate-level representation comprises a gate-level implementation of a functional block of a functional-level representation of the quantum circuit, wherein the functional block defines an operation of the quantum circuit over at least two cycles;
obtaining metadata from a functional-level processing component, wherein the metadata comprise an artifact associated with the gate-level implementation of the functional block; and
compiling the gate-level representation of the quantum circuit, wherein said compiling is performed based on the metadata.