	US 12,086,653 B2
	Software visible and controllable lock-stepping with configurable logical processor granularities
Vedvyas Shanbhogue, Austin, TX (US); Jeff A. Huxel, Austin, TX (US); Jeffrey G. Wiedemeier, Austin, TX (US); James D. Allen, Austin, TX (US); Arvind Raman, Austin, TX (US); and Krishnakumar Ganapathy, Bee Cave, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 24, 2020, as Appl. No. 17/134,065.
Prior Publication US 2022/0206875 A1, Jun. 30, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/52 (2006.01); G06F 11/07 (2006.01); G06F 11/16 (2006.01); G06F 9/455 (2018.01)

CPC G06F 9/52 (2013.01) [G06F 9/30101 (2013.01); G06F 9/3885 (2013.01); G06F 11/0724 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 11/1629 (2013.01); G06F 11/1683 (2013.01); G06F 9/45558 (2013.01)]

24 Claims

1. An apparatus, comprising:

first model specific register (MSR) space to specify a granularity of a processing entity of a lock-step group of processing entities;

second MSR space to specify whether the processing entity is an active or shadow processing entity of the lock-step group of processing entities; and,

third MSR space to indicate that the lock-step group of processing entities is active;

wherein, the first MSR space, the second MSR space and the third MSR space is accessible to at least one of a virtual machine monitor, an operating system and an application software program.