US 12,086,644 B2
Logical slot to hardware slot mapping for graphics processors
Andrew M. Havlir, Orlando, FL (US); Steven Fishwick, St Albans (GB); David A. Gotwalt, Winter Springs, FL (US); Benjamin Bowman, London (GB); Ralph C. Taylor, Deland, FL (US); Melissa L. Velez, Orlando, FL (US); Mladen Wilder, Cambridge (GB); Ali Rabbani Rankouhi, Bushey (GB); and Fergus W. MacGarry, Cambridge (GB)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 11, 2021, as Appl. No. 17/399,711.
Prior Publication US 2023/0050061 A1, Feb. 16, 2023
Int. Cl. G06F 3/00 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06F 9/5044 (2013.01) [G06F 9/4881 (2013.01); G06F 9/505 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising a graphics processor that includes:
circuitry that implements a plurality of logical slots;
a set of graphics processor sub-units that each implement multiple distributed hardware slots, wherein:
a given distributed hardware slot includes work queue circuitry configured to store graphics work and configuration registers corresponding to the stored graphics work; and
a given graphics processor sub-unit includes shader processor circuitry configured to execute instructions specified by stored graphics work in the sub-unit's multiple distributed hardware slots; and
control circuitry configured to:
assign first and second sets of graphics work to first and second logical slots;
determine a first distribution rule for the first set of graphics work that indicates to distribute to all of the graphics processor sub-units in the set;
determine a second distribution rule for the second set of graphics work that indicates to distribute to fewer than all of the graphics processor sub-units in the set;
determine a mapping between the first logical slot and a first set of one or more distributed hardware slots based on the first distribution rule;
determine a mapping between the second logical slot and a second set of one or more distributed hardware slots based on the second distribution rule; and
distribute the first and second sets of graphics work to the work queue circuitry of one or more of the graphics processor sub-units according to the determined mappings;
wherein the graphics processor sub-units are configured to execute the distributed first and second sets of graphics work using their respective shader processor circuitry.