US 12,086,603 B2
Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
Eran Shifer, Tel Aviv (IL); Mostafa Hagog, Kaukab (IL); and Eliyahu Turiel, Shimshit (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 27, 2022, as Appl. No. 17/975,596.
Application 17/975,596 is a continuation of application No. 17/216,618, filed on Mar. 29, 2021, granted, now 11,494,194.
Application 17/216,618 is a continuation of application No. 16/059,001, filed on Aug. 8, 2018, granted, now 10,963,263, issued on Mar. 30, 2021.
Application 16/059,001 is a continuation of application No. 15/426,276, filed on Feb. 7, 2017, granted, now 10,061,593, issued on Aug. 28, 2018.
Application 15/426,276 is a continuation of application No. 13/629,460, filed on Sep. 27, 2012, granted, now 9,582,287, issued on Feb. 28, 2017.
Prior Publication US 2023/0052630 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 15/80 (2006.01)
CPC G06F 9/3887 (2013.01) [G06F 9/30076 (2013.01); G06F 9/3879 (2013.01); G06F 15/8007 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of digital signal processing (DSP) cores, including a DSP core, the DSP core comprising:
decode circuitry to decode instructions of a first thread and a second thread;
execution circuitry to execute at least some of the instructions of the first thread and the second thread; and
a register file to store context data for the first thread and the second thread;
shared vector processing circuitry coupled to and shared by the plurality of DSP cores, the shared vector processing circuitry comprising:
a first plurality of registers to store first context data associated with the first thread;
a second plurality of registers to store second context data associated with the second thread; and
vector execution circuitry to execute single instruction multiple data (SIMD) instructions of the first thread and the second thread; and
memory management circuitry to translate virtual addresses within a virtual address space shared by the plurality of DSP cores and the shared vector processing circuitry, the virtual addresses to be translated to physical addresses of a system memory.