US 12,086,602 B2
Scheduling of threads for execution utilizing load balancing of thread groups
Balaji Vembu, Folsom, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Joydeep Ray, Folsom, CA (US); and Altug Koker, El Dorado Hills, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 4, 2023, as Appl. No. 18/365,595.
Application 18/365,595 is a continuation of application No. 17/848,559, filed on Jun. 24, 2022, granted, now 11,768,687.
Application 17/848,559 is a continuation of application No. 17/173,923, filed on Feb. 11, 2021, granted, now 11,397,585, issued on Jul. 26, 2022.
Application 17/173,923 is a continuation of application No. 16/825,129, filed on Mar. 20, 2020, granted, now 10,922,085, issued on Feb. 16, 2021.
Application 16/825,129 is a continuation of application No. 16/388,444, filed on Apr. 18, 2019, granted, now 10,599,438, issued on Mar. 24, 2020.
Application 16/388,444 is a continuation of application No. 15/477,017, filed on Apr. 1, 2017, granted, now 10,310,861, issued on Jun. 4, 2019.
Prior Publication US 2024/0086199 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 1/20 (2006.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 9/52 (2006.01); G06F 9/54 (2006.01); G06F 12/0842 (2016.01); G06F 12/0866 (2016.01); G06F 12/0897 (2016.01); G06F 15/16 (2006.01); G06F 15/76 (2006.01); G06T 1/60 (2006.01)
CPC G06F 9/3851 (2013.01) [G06F 9/46 (2013.01); G06F 9/4843 (2013.01); G06F 9/4881 (2013.01); G06F 9/5027 (2013.01); G06F 9/522 (2013.01); G06F 9/545 (2013.01); G06F 12/0842 (2013.01); G06F 12/0866 (2013.01); G06F 12/0897 (2013.01); G06F 15/16 (2013.01); G06F 15/76 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06F 2209/5018 (2013.01); G06T 2200/28 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of multiprocessors, each multiprocessor including a plurality of cores for execution of multiple threads, the multiple threads comprising a plurality of thread groups;
a memory for thread processing; and
scheduling hardware, the scheduling hardware to schedule the multiple threads among the plurality of multiprocessors;
wherein the processor is to:
determine a magnitude of barriers used in each of the plurality of thread groups,
determine barrier weight values based on the determined magnitude of barriers used in each of the plurality of thread groups, and store the determined barrier weight values, and
schedule the threads of the plurality of thread groups to the plurality of multiprocessors based at least in part on the determined barrier weight values.