US 12,086,600 B2
Branch target buffer with shared target bits
Somasundaram Arunachalam, Raleigh, NC (US); Daren Eugene Streett, Cary, NC (US); and Richard William Doing, Raleigh, NC (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Dec. 5, 2022, as Appl. No. 18/061,951.
Prior Publication US 2024/0184587 A1, Jun. 6, 2024
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01)
CPC G06F 9/3844 (2013.01) [G06F 9/30145 (2013.01); G06F 9/322 (2013.01); G06F 9/3806 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A processor comprising:
a front end, the front end comprising:
a branch predictor, the branch predictor comprising a branch target buffer comprising a plurality of branch targets, at least one of the branch targets comprising branch target bits specifying a portion of a branch destination address; and
a fetch target queue; and
a processor back end,
wherein the branch target buffer comprises shared bits, wherein different portions of the shared bits are used together with different branch targets to specify the branch destination address.