US 12,086,596 B2
Instructions for accelerating Keccak execution in a processor
Christoph Dobraunig, St. Veit an der Glan (AT); Santosh Ghosh, Hillsboro, OR (US); and Manoj Sastry, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 6, 2023, as Appl. No. 18/164,738.
Prior Publication US 2024/0264837 A1, Aug. 8, 2024
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30196 (2013.01) [G06F 9/30029 (2013.01); G06F 9/30032 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus comprising:
decoder circuitry to decode a conditional rotate and exclusive-OR (XOR) operation instruction, the conditional rotate and XOR instruction to include a field for an opcode, a first operand, a second operand, a third operand, and a fourth operand, the opcode to indicate execution circuitry is to perform a conditional rotate and XOR operation; and
execution circuitry to execute the conditional rotate and XOR instruction according to the opcode to perform the conditional rotate and XOR operation to:
left rotate the third operand by a first rotation value to generate a first result, execute the first operand XOR the second operand XOR the first result to generate a second result, left rotate the second result by a second rotation value to generate a third result, and store the third result in the first operand.