US 12,086,595 B2
Apparatuses, methods, and systems for instructions for downconverting a tile row and interleaving with a register
Menachem Adelman, Haifa (IL); Robert Valentine, Kiryat Tivon (IL); Amit Gradstein, Binyamina (IL); Daniel Towner, Bath (GB); and Mark Charney, Lexington, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 27, 2021, as Appl. No. 17/214,853.
Prior Publication US 2022/0308873 A1, Sep. 29, 2022
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/3016 (2013.01) [G06F 9/30025 (2013.01); G06F 9/30098 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus comprising:
decoding circuitry to decode a single instruction, the instruction having one or more fields to specify an opcode, one or more fields to specify a location of a first source operand, one or more fields to specify a location of a second source operand, one or more fields to specify a location of a destination operand, and one or more fields to specify an index value to be used to index a row in the first source operand, wherein the opcode is to indicate execution circuitry is to downconvert data elements of the indexed row of the first source operand, interleave the downconverted elements with data elements of the second source operand, and store the interleaved elements in the destination operand; and
execution circuitry to execute the decoded instruction according to the opcode.