US 12,086,592 B2
Processor, processing method, and related device for accelerating graph calculation
Xiping Zhou, Shenzhen (CN); Ruoyu Zhou, Shenzhen (CN); Fan Zhu, Shenzhen (CN); and Wenbo Sun, Hangzhou (CN)
Assigned to Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Guangdong (CN)
Filed on Nov. 29, 2022, as Appl. No. 18/070,781.
Application 18/070,781 is a continuation of application No. PCT/CN2020/093627, filed on May 30, 2020.
Prior Publication US 2023/0093393 A1, Mar. 23, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30076 (2013.01) [G06F 9/30087 (2013.01); G06F 9/3836 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A processor, comprising:
a memory;
a processor core, wherein the processor core comprises an instruction dispatching circuit, a graph flow circuit and at least one general-purpose operation circuit that are connected to the instruction dispatching circuit, wherein
the instruction dispatching circuit is configured to:
allocate a general-purpose calculation instruction to at least one general-purpose calculation circuit, and
allocate a graph calculation control instruction to a graph flow circuit, wherein the general-purpose calculation instruction instructs the processor to execute a general-purpose calculation task, and the graph calculation control instruction instructs the processor to execute a graph calculation task:
the at least one general-purpose operation circuit is configured to execute the general-purpose calculation instruction;
the graph flow circuit is configured to:
execute the graph calculation control instruction, wherein the graph calculation control instruction comprises a graph calculation start instruction and a graph build start instruction, and wherein the graph build start instruction carries a target address in the memory;
receive the graph build start instruction;
read graph build block information from the memory based on the target address, wherein the graph flow circuit comprises N calculation nodes, and wherein the graph build block information comprises an operation method of each of the N calculation nodes and connection and sequence information of the N calculation nodes;
check whether the graph build block information is consistent with an address of a pre-started graph build block;
determine whether input parameters in M calculation nodes have been input; and
in response to determining that the graph build block information is consistent with the address of the pre-started graph build block and the input parameters in the M calculation nodes have been input, execute the graph calculation task.