US 12,086,591 B2
Device, method and system to predict an address collision by a load and a store
Sudhanshu Shukla, Bengaluru (IN); Jayesh Gaur, Bangalore (IN); Stanislav Shwartsman, Haifa (IL); and Pavel I. Kryukov, Moscow (RU)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/214,698.
Prior Publication US 2022/0308876 A1, Sep. 29, 2022
Int. Cl. G06F 9/22 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30043 (2013.01) [G06F 9/3856 (2023.08)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
manager circuitry to:
detect an address collision event wherein a memory address is targeted by both a first load instruction of a first instruction type and a first store instruction of a second instruction type, wherein the first instruction type and the second instruction type correspond to different respective instruction pointer values; and
determine, based on the address collision event, a count of decisions each to forego a reversal of an order of execution of a respective instruction of the first instruction type and a respective instruction of the second instruction type;
classification circuitry to perform an evaluation of the count based on a threshold maximum count value; and
prediction circuitry, coupled to the classification circuitry, to generate, based on the evaluation, a signal to determine an order of execution of a second load instruction of the first instruction type and a second store instruction of the second instruction type.