US 12,086,568 B2
High throughput parallel architecture for recursive sinusoid synthesizer
Ankur Bal, Greater Noida (IN); and Rupesh Singh, Ghaziabad (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Apr. 14, 2023, as Appl. No. 18/134,737.
Application 18/134,737 is a division of application No. 16/988,912, filed on Aug. 10, 2020, granted, now 11,656,848.
Claims priority of provisional application 62/902,006, filed on Sep. 18, 2019.
Prior Publication US 2023/0251829 A1, Aug. 10, 2023
Int. Cl. G06F 7/544 (2006.01); G06F 7/548 (2006.01); H03K 3/037 (2006.01); H03K 5/01 (2006.01); H03K 5/00 (2006.01)
CPC G06F 7/548 (2013.01) [G06F 7/5443 (2013.01); H03K 3/037 (2013.01); H03K 5/01 (2013.01); H03K 2005/00078 (2013.01)] 29 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first multiplier configured to multiply a first input with a first coefficient;
a first adder configured to generate a first output from a sum of an output of the first multiplier and a second input;
a second multiplier configured to multiply a third input with a second coefficient;
wherein the second coefficient is a negative of the first coefficient;
a third multiplier configured to multiply a fourth input with a third coefficient;
a second adder configured to generate a second output from a sum of outputs of the second and third multipliers;
wherein the second and third inputs are derived from the first output; and
wherein the first and fourth inputs are derived from the second output.