US 12,086,529 B1
Circuit design modification using timing-based yield calculation
Igor Keller, Pleasanton, CA (US); Eric K. Anderson, Livermore, CA (US); and Yang Gao, San Jose, CA (US)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Mar. 10, 2022, as Appl. No. 17/691,974.
Int. Cl. G06F 30/398 (2020.01); G06F 30/3315 (2020.01); G06F 119/02 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/3315 (2020.01); G06F 2119/02 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable medium comprising instructions that, when executed by a hardware processor of a device, cause the device to perform operations comprising:
accessing data that describes a circuit design for an integrated circuit;
generating a current set of yield probability values for the circuit design based on static timing analysis data for the circuit design;
generating path description data that describes a set of paths of the circuit design used in the generating of the current set of yield probability values, and describes a set of yield probability loss values associated with the set of paths;
determining whether the circuit design exceeds a set of limits for the circuit design; and
in response to determining that the circuit design does not exceed any limit in the set of limits, modifying one or more cell instances of the circuit design based on the current set of yield probability values and the path description data.