US 12,086,527 B2
Electrical design rule checking method and device for integrated circuit
Yaquan Tang, Shanghai (CN)
Assigned to SPREADTRUM COMMUNICATIONS (SHANGHAI) CO., LTD., Shanghai (CN)
Appl. No. 17/426,612
Filed by SPREADTRUM COMMUNICATIONS (SHANGHAI) CO., LTD., Shanghai (CN)
PCT Filed Mar. 5, 2019, PCT No. PCT/CN2019/077021
§ 371(c)(1), (2) Date Jul. 28, 2021,
PCT Pub. No. WO2020/155290, PCT Pub. Date Aug. 6, 2020.
Claims priority of application No. 201910081729.9 (CN), filed on Jan. 28, 2019.
Prior Publication US 2022/0100946 A1, Mar. 31, 2022
Int. Cl. G06F 30/398 (2020.01); G06F 30/323 (2020.01); G06F 30/392 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/323 (2020.01); G06F 30/392 (2020.01)] 9 Claims
OG exemplary drawing
 
1. A method for electrical design rule check (DRC) of an integrated circuit, the method comprising:
acquiring a parasitic parameter netlist of the integrated circuit;
receiving a circuit simulation result of the integrated circuit and electrical DRC rules;
determining, based on the parasitic parameter netlist and the electrical DRC rules of the integrated circuit, whether the integrated circuit complies with the electrical DRC rules, and
determining, based on the circuit simulation result, a physical location in the integrated circuit that does not comply with the electrical DRC rules in response to determining that the integrated circuit does not comply with the electrical DRC rules.