US 12,086,526 B2
Methods and devices of correcting layout for semiconductor processes using machine learning
Sooyong Lee, Yongin-si (KR); Jeeyong Lee, Anyang-si (KR); Seunghune Yang, Seoul (KR); and Hyeyoung Ji, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Yongin-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 20, 2021, as Appl. No. 17/380,200.
Claims priority of application No. 10-2020-0166853 (KR), filed on Dec. 2, 2020.
Prior Publication US 2022/0171913 A1, Jun. 2, 2022
Int. Cl. G06F 30/398 (2020.01); G06N 20/00 (2019.01)
CPC G06F 30/398 (2020.01) [G06N 20/00 (2019.01)] 18 Claims
OG exemplary drawing
 
1. A method of correcting a layout for semiconductor processes, comprising:
receiving a layout, wherein the layout comprises schematic information for semiconductor processes to form process patterns of a semiconductor device, and further comprises a plurality of layout patterns,
with respect to each layout pattern of the plurality of layout patterns included in the layout, determining vertical features indicating an effect of a lower structure on the process patterns, wherein the lower structure is a structure that is formed in the semiconductor device before the process patterns are formed, and wherein the vertical features include depth positions of the lower structure with respect to the layout pattern;
training a machine learning module based on a training layout and the vertical features of the training layout;
inferring an after-cleaning inspection (ACI) result using the machine learning model based on the vertical features; and
correcting a design layout based on the ACI result, wherein the design layout comprises schematic information to form target process patterns.