CPC G06F 30/392 (2020.01) [G06F 30/3947 (2020.01); H01L 27/0207 (2013.01); G06F 2111/20 (2020.01); G06F 2119/06 (2020.01)] | 18 Claims |
1. A method for designing a chip fabric comprising:
instantiating a first plurality of rows in a first region of a fabric, the first region having a height corresponding to a sum of heights of the first plurality of rows;
instantiating a second plurality of rows in a second region of the fabric, the second region horizontally adjacent to the first region in the fabric, the second region having a height corresponding to a sum of heights of the second plurality of rows;
determining, by a processing device, whether a row of the first plurality of rows is misaligned with a row of the second plurality of rows;
adding a transition region between the row of the first plurality of rows and the row of the second plurality of rows in response to determining that the row of the first plurality of rows is misaligned with the row of the second plurality of rows; and
removing a transition region between a set of rows in the first region and a set of rows in the second region in response to a determination that the set of rows in the first region and the set of rows in the second region are aligned.
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