US 12,086,521 B2
Circuit design simulation and clock event reduction
Tharun Kumar Ksheerasagar, Telangana (IN); Rohit Bhadana, Faridabad (IN); Hemant Kashyap, Hyderabad (IN); and Pratyush Ranjan, Patna (IN)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Oct. 7, 2021, as Appl. No. 17/496,198.
Prior Publication US 2023/0114858 A1, Apr. 13, 2023
Int. Cl. G06F 30/3312 (2020.01); G06F 30/327 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 30/327 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
detecting, using computer hardware, a first model and a second model of a circuit design driven by a clock source through a clock channel configured to convey clock events specifying a clock signal;
wherein a clock requirement of the first model for a simulation of the circuit design differs from a clock requirement of the second model for the simulation; and
modifying, using the computer hardware, an interface of the first model based on the clock requirement of the first model by disconnecting the first model from the clock channel and inserting, into the circuit design, a virtual channel formed of a further clock source and a clock sink that couples to the first model;
wherein the virtual channel is configured to convey, to the first model, clock information specified by the clock requirement of the first model.