US 12,086,468 B2
Split protocol approaches for enabling devices with enhanced persistent memory region access
Luca Bert, San Jose, CA (US); and Joseph H. Steinmetz, Loomis, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 23, 2023, as Appl. No. 18/200,851.
Application 18/200,851 is a continuation of application No. 17/147,834, filed on Jan. 13, 2021, granted, now 11,704,060.
Claims priority of provisional application 63/127,213, filed on Dec. 18, 2020.
Prior Publication US 2023/0297286 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory; and
a processing device, operatively coupled with the memory, to perform operations comprising:
receiving a host command designating a first interface standard at a first port for exposing a storage element implemented by a non-volatile memory device and a second interface standard at a second port for exposing a persistent memory region (PMR) implemented as a power protected region of a volatile memory device, wherein the non-volatile memory device and the volatile memory device are associated with a first switch for implementing the first interface standard and a second switch for implementing the second interface standard, and wherein the first interface standard supports one or more alternate protocols implemented by the second interface standard;
exposing the storage element by designating the first interface standard at the first port and the PMR by designating the second interface standard at the second port; and
allocating a segment of the PMR as a cacheable memory marked as visible through the second interface standard, wherein the segment of the PMR is shared through the second interface standard.